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datasheet 4-output very low power pcie gen 1-2-3-4 clock generator 9fgv0431 idt? 4-output very low power pcie gen 1-2-3-4 clock generator 1 9fgv0431 june 22, 2017 description the 9fgv0431 is a 4-output very low-power clock generator for pcie gen 1, 2, 3 and 4 applications. the device has 4 output enables for clock management and supports 2 different spread spectrum levels in addition to spread off. recommended application pcie gen1-4 clock generation for riser cards, storage, networking, jbod, communications, access points output features ? 4 ? 0.7v low-power hcsl-compatible (lp-hcsl) dif pairs ? 1 ? 1.8v lvcmos ref output w/wake-on-lan key specifications ? dif cycle-to-cycle jitter <50ps ? dif output-to-output skew <50ps ? dif phase jitter is pcie gen1-2-3-4 compliant ? ref phase jitter is < 1.5ps rms features/benefits ? 1.8v operation; reduced power consumption ? oe# pins; support dif power management ? lp-hcsl differential clock outputs; reduced power and board space ? programmable slew rate for each output; allows tuning for various line lengths ? programmable output amplitude; allows tuning for various application environments ? dif outputs blocked until pll is locked; clean system start-up ? selectable 0%, -0.25% or -0.5% spread on dif outputs; reduces emi ? external 25mhz crystal; supports tight ppm with 0 ppm synthesis error ? configuration can be accomplished with strapping pins; smbus interface not required for device control ? 3.3v tolerant smbus inte rface works with legacy controllers ? space saving 32-pin 5x5 mm mlf; minimal board space ? selectable smbus addresses; multiple devices can easily share an smbus segment block diagram x1_25 x2 dif(3:0) control logic ss_en_tri ckpwrgd_pd# sdata_3.3 ss capable pll 4 osc r e f 1 . 8 oe(3:0)# sclk_3.3 sadr
9fgv0431 4-output very low power pcie gen 1-2-3-4 clock generator idt? 4-output very low power pcie gen 1-2-3-4 clock generator 2 9fgv0431 june 22, 2017 pin configuration smbus address selection table power management table power connections vss_en_tri ^ckpwrgd_pd# gnd voe3# dif3# dif3 gnd vddo1.8 32 31 30 29 28 27 26 25 gndxtal 1 24 voe2# xin/clkin_25 2 23 dif2# x2 3 22 dif2 vddxtal1.8 4 21 vdda1.8 vddref1.8 5 20 gnda vsadr/ref1.8 6 19 dif1# gndref 7 18 dif1 gnddig 817voe1# 9 10111213141516 vdddig1.8 sclk_3.3 sdata_3.3 voe0# dif0 dif0# gnd vddo1.8 32-pin mlf, 5x5 mm, 0.5mm pitch v prefix indicates internal 120kohm pull down resistor 9fgv0431 ^ prefix indicates internal 120kohm pull up resisto r sadr address 0 1101000 1 1101010 + read/write bit x x state of sadr on first application of ckpwrgd_pd# oex# true o/p comp. o/p 0xxlowlow hi-z 1 1 1 0 running running running 1 0 1 low low low ref ckpwrgd_pd# smbus oe bit difx 1. ref is hi-z until the 1st assertion of ckpwrgd_pd# high. after this, when ckpwrg_pd# is low, ref is low. pin number vdd gnd 41 57 98, 30 16, 25 15, 26 21 20 pll analog ref output description xtal analo g di g ital power dif outputs
9fgv0431 4-output very low power pcie gen 1-2-3-4 clock generator idt? 4-output very low power pcie gen 1-2-3-4 clock generator 3 9fgv0431 june 22, 2017 pin descriptions pin# pin name type pin description 1 gndxtal gnd gnd for xtal 2 xin/clkin_25 in crystal input or reference clock input. nominally 25mhz. 3 x2 out crystal output. 4 vddxtal1.8 pwr power supply for xtal, nominal 1.8v 5 vddref1.8 pwr vdd for ref output. nominal 1.8v. 6 vsadr/ref1.8 latched i/o latch to select smbus address/1.8v lvcmos copy of x1 pin. 7 gndref gnd ground pin for the ref outputs. 8 gnddig gnd ground pin for digital circuitry 9 vdddig1.8 pwr 1.8v digital power (dirty power) 10 sclk_3.3 in clock pin of smbus circuitry, 3.3v tolerant. 11 sdata_3.3 i/o data pin for smbus circuitry, 3.3v tolerant. 12 voe0# in active low input for enabling dif pair 0. this pin has an internal pull-down. 1 =disable outputs, 0 = enable outputs 13 dif0 out differential true clock output 14 dif0# out differential complementary clock output 15 gnd gnd ground pin. 16 vddo1.8 pwr power supply for outputs, nominally 1.8v. 17 voe1# in active low input for enabling dif pair 1. this pin has an internal pull-down. 1 =disable outputs, 0 = enable outputs 18 dif1 out differential true clock output 19 dif1# out differential complementary clock output 20 gnda gnd ground pin for the pll core. 21 vdda1.8 pwr 1.8v power for the pll core. 22 dif2 out differential true clock output 23 dif2# out differential complementary clock output 24 voe2# in active low input for enabling dif pair 2. this pin has an internal pull-down. 1 =disable outputs, 0 = enable outputs 25 vddo1.8 pwr power supply for outputs, nominally 1.8v. 26 gnd gnd ground pin. 27 dif3 out differential true clock output 28 dif3# out differential complementary clock output 29 voe3# in active low input for enabling dif pair 3. this pin has an internal pull-down. 1 =disable outputs, 0 = enable outputs 30 gnd gnd ground pin. 31 ^ckpwrgd_pd# in input notifies device to sample latched inputs and start up on first high assertion. low enters power down mode, subsequent high assertions exit power down mode. this pin has internal pull-up resistor. 32 vss_en_tri latched in latched select input to select spread spectrum amount at initial power up : 1 = -0.5% spread, m = -0.25%, 0 = spread off
9fgv0431 4-output very low power pcie gen 1-2-3-4 clock generator idt? 4-output very low power pcie gen 1-2-3-4 clock generator 4 9fgv0431 june 22, 2017 test loads alternate terminations alternate differential output terminations rs zo units 33 100 27 85 ohms rs rs low-power differential output test load 2pf 2pf 5 inches zo=100ohms ref output 33 ref output test load 5pf zo = 50 ohms lvds clk input zo r8b r7b r8a r7a 3.3 volts cc cc rs rs driving lvds driving lvds inputs with the 9fgv 0431 receiver has termination receiver does not have termination r7a, r7b 10k ohm 140 ohm r8a, r8b 5.6k ohm 75 ohm cc 0.1 uf 0.1 uf vcm 1.2 volts 1.2 volts component value note
9fgv0431 4-output very low power pcie gen 1-2-3-4 clock generator idt? 4-output very low power pcie gen 1-2-3-4 clock generator 5 9fgv0431 june 22, 2017 absolute maximum ratings stresses above the ratings listed below can cause permanent damage to the 9fgv0431. these ratings, which are standard values for idt commercially rated parts, are stress ratings only. functional operati on of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for ex tended periods can affe ct product reliability. electrical parameters are guar anteed only over the recommended operating temperature range. electrical characterist ics?current consumption electrical characteristics? output duty cycle, jitter , and skew characteristics parameter symbol conditions min typ max units notes 1.8v supply voltage vddx1.8 applies to all vdd pins -0.5 2.5 v 1,2 input voltage v in -0.5 v dd +0.3v v 1, 3 input high voltage, smbus v ihsmb smbus clock and data pins 3.6v v 1 storage temperature ts -65 150 c 1 junction temperature tj 125 c 1 input esd protection esd prot human body model 2000 v 1 1 guaranteed by design and characterization, not 100% tested in production. 2 operation under these conditions is neither implied nor guaranteed. 3 not to exceed 2.5v. ta = t com or t ind; supply voltage per vdd of normal operation conditions, see test loads for loading conditions parameter symbol conditions min typ max units notes i ddaop vdda, all outputs active @100mhz 68 ma 1 i ddop vdd, all outputs active @100mhz 26 30 ma 1 suspend supply current i ddsusp vddxxx, pd# = 0, wake-on-lan enabled 68 ma 1 powerdown current i ddpd pd#=0 0.6 1 ma 1, 2 1 guaranteed by design and characterization, not 100% tested in production. 2 assuming ref is not running in power down state operating supply current ta = t com or t ind; supply voltage per vdd of normal operation conditions, see test loads for loading conditions parameter symbol conditions min typ max units notes duty cycle t dc measured differentially, pll mode 45 50.1 55 % 1 skew, output to output t sk3 v t = 50% 37 50 ps 1 jitter, cycle to cycle t jcyc-cyc pll mode 12 50 ps 1,2 1 guaranteed by design and characterization, not 100% tested in production. 2 measured from differential waveform
9fgv0431 4-output very low power pcie gen 1-2-3-4 clock generator idt? 4-output very low power pcie gen 1-2-3-4 clock generator 6 9fgv0431 june 22, 2017 electrical characteristics?input/supp ly/common parameters ?normal operating conditions ta = t com or t ind; supply voltage per vdd of normal operation conditions, see test loads for loading conditions parameter symbol conditions min typ max units notes 1.8v supply voltage vdd x 1.8 supply voltage for core, analog and single-ended lvcmos outputs 1.7 1.8 1.9 v 1 t com commercial range 0 25 70 c 1 t ind industrial range -40 25 85 c 1 input high voltage v ih single-ended inputs, except smbus 0.75 v dd v dd + 0.3 v 1 input mid voltage v im single-ended tri-level inputs ('_tri' suffix, if present) 0.4 v dd 0.6 v dd v1 input low voltage v il single-ended inputs, except smbus -0.3 0.25 v dd v1 schmitt trigger positive going threshold voltage v t+ single-ended inputs, where indicated 0.4 v dd 0.7 v dd v1 schmitt trigger negative goin g threshold volta g e v t- single-ended inputs, where indicated 0.1 v dd 0.4 v dd v1 hysteresis voltage v h v t+ - v t- 0.1 v dd 0.4 v dd v1 output high voltage v ih single-ended outputs, except smbus. i oh = -2ma v dd -0.45 v 1 output low voltage v il single-ended outputs, except smbus. i ol = -2ma 0.45 v 1 i in single-ended inputs, v in = gnd, v in = vdd -5 5 ua 1 i inp single-ended inputs v in = 0 v; inputs with internal pull-up resistors v in = vdd; inputs with internal pull-down resistors -200 200 ua 1 input frequency f in xtal, or x1 input 23 25 27 mhz 1 pin inductance l p in 7nh1 c in logic inputs, except dif_in 1.5 5 pf 1 c out output pin capacitance 6 pf 1 clk stabilization t stab from v dd power-up and after input clock stabilization or de-assertion of pd# to 1st clock 0.6 1.8 ms 1,2 ss modulation frequency f mod allowable frequency (triangular modulation) 31 31.6 32 khz 1 oe# latency t latoe# dif start after oe# assertion dif stop after oe# deassertion 123clocks1,3 tdrive_pd# t drvpd dif output enable after pd# de-assertion 300 us 1,3 tfall t f fall time of single-ended control inputs 5 ns 1,2 trise t r rise time of single-ended control inputs 5 ns 1,2 smbus input low voltage v ilsmb v ddsmb = 3.3v, see note 4 for v ddsmb < 3.3v 0.8 v 1,4 smbus input high voltage v ihsmb v ddsmb = 3.3v, see note 5 for v ddsmb < 3.3v 2.1 3.6 v 1,5 smbus output low voltage v olsmb @ i pullup 0.4 v 1 smbus sink current i pullup @ v ol 4ma1 nominal bus voltage v ddsmb 1.7 3.6 v 1 sclk/sdata rise time t rsmb (max vil - 0.15) to (min vih + 0.15) 1000 ns 1 sclk/sdata fall time t fsmb (min vih + 0.15) to (max vil - 0.15) 300 ns 1 smbus operating frequency f maxsmb maximum smbus operating frequency 400 khz 1 1 guaranteed by design and characterization, not 100% tested in production. 2 control input must be monotonic from 20% to 80% of input swing. 5 for v ddsmb < 3.3v, v ihsmb >= 0.65v ddsmb capacitance 3 time from deassertion until outputs are >200 mv 4 for v ddsmb < 3.3v, v ilsmb <= 0.35v ddsmb input current ambient operating temperature
9fgv0431 4-output very low power pcie gen 1-2-3-4 clock generator idt? 4-output very low power pcie gen 1-2-3-4 clock generator 7 9fgv0431 june 22, 2017 electrical characteristics?di f 0.7v low power hcsl output electrical characteristics?filtered ph ase jitter parameters - pcie common clocked (cc) architectures ta = t com or t ind; supply voltage per vdd of normal operation conditions, see test loads for loading conditions parameter symbol conditions min typ max units notes scope avera g in g on 3.0v/ns settin g 2.6 3.5 4.6 v/ns 1, 2, 3 scope averaging on 2.0v/ns setting 1.5 2.5 3.5 v/ns 1, 2, 3 slew rate matching trf slew rate matching, scope averaging on 8 20 % 1,2,4 voltage high v hi gh 660 797 850 1,8 voltage low v low -150 15 150 1 max voltage vmax 833 1150 1 min voltage vmin -300 -41 1 vswin g vswin g scope avera g in g off 300 1564 mv 1,2 crossing voltage (abs) vcross_abs scope averaging off 300 427 550 mv 1,5 crossing voltage (var) -vcross scope averaging off 15 140 mv 1,6 2 measured from differential waveform 7 at default smbus settings. 6 the total variation of all vcross measurements in any particular system. note that this is a subset of vcross_min/max (vcross absolute) allowed. the intent is to limit vcross induced modulation by setting -vcross to be smaller than vcross absolute. 1 guaranteed by design and characterization, not 100% tested in production. c l = 2pf with r s = 33 ? for zo = 50 ? (100 ? differential trace impedance). 3 slew rate is measured through the vswing voltage range centered around differential 0v. this results in a +/-150mv window arou nd differential 0v. statistical measurement on single-ended signal using oscilloscope math function. (scope averaging on) mv measurement on single ended signal using absolute value. (scope averaging off) mv 4 matching applies to rising edge rate for clock and fa lling edge rate for clock#. it is measured using a +/-75mv window centered on the average cross point where clock rising meets clock# falling. the median cross point is used to calculate the voltage thresh olds the oscilloscope is to use for the edge rate calculations. 5 vcross is defined as voltage where clock = clock# measured on a component test board and only applies to the differential risi ng edge (i.e. clock rising and clock# fa lling). slew rate trf t amb = over the specified operating range. supply voltages per normal operation conditions, see test loads for loading conditions symbol parameter conditions min typ max specification limit units notes t jphpcieg1-cc pcie gen 1 21 25 35 86 ps (p-p) 1, 2, 3 pcie gen 2 low band 10khz < f < 1.5mhz (pll bw of 5-16mhz, 8-16mhz, cdr = 5mhz) 0.9 0.9 1.1 3 ps (rms) 1, 2 pcie gen 2 high band 1.5mhz < f < nyquist (50mhz) (pll bw of 5-16mhz, 8-16mhz, cdr = 5mhz) 1.5 1.6 1.9 3.1 ps (rms) 1, 2 t jphpcieg3-cc pcie gen 3 (pll bw of 2-4mhz, 2-5mhz, cdr = 10mhz) 0.3 0.37 0.44 1 ps (rms) 1, 2 t jphpcieg4-cc pcie gen 4 (pll bw of 2-4mhz, 2-5mhz, cdr = 10mhz) 0.3 0.37 0.44 0.5 ps (rms) 1, 2 notes on pcie filtered phase jitter table. 1 applies to all differential outputs, guaranteed by design and characterization. 2 calculated from intel-supplied clock jitter tool, with spread on and off. 3 sample size of at least 100k cycles. this figure extr apolates to 108ps pk-pk at 1m cycles for a ber of 1 -12 . phase jitter, pll mode t jphpcieg2-cc
9fgv0431 4-output very low power pcie gen 1-2-3-4 clock generator idt? 4-output very low power pcie gen 1-2-3-4 clock generator 8 9fgv0431 june 22, 2017 electrical characteristics?ref clock periods?differential outputs with spread spectrum disabled clock periods?differential outputs wi th -0.5% spread spectrum enabled ta = t com or t ind ; supply voltage per vdd of normal operation conditions, see test loads for loading conditions parameter symbol conditions min typ max units notes long accuracy ppm see tperiod min-max values ppm 1,2 clock period t p eriod 25 mhz output nominal 40 ns 1,2 rise/fall slew rate t rf1 v oh = vdd-0.45v, v ol = 0.45v 0.5 1.3 2.5 v/ns 1,3 duty cycle d tcd v t = vdd/2 v 455355%1,4 duty cycle distortion d t1 v t = vdd/2 v 0 2 3 % 1,5 jitter, cycle to cycle t j c y c-c y c v t = vdd/2 v 20 250 ps 1,4 noise floor t j dbc1k 1khz offset -125 -119 dbc 1,4 noise floor t j dbc10k 10khz offset to nyquist -140 -120 dbc 1,4 jitter, phase t jphref 12khz to 5mhz 0.81 1.5 ps (rms) 1,4 1 guaranteed by design and characterization, not 100% tested in production. 3 typical value occurs when ref slew rate is set to default value 4 when driven by a crystal. 5 when driven by an external oscillator via the x1 pin. x2 should be floating in this case. 2 all long term accuracy and clock period specifications are guaranteed assuming that ref is trimmed to 25.00 mhz 0 1 clock 1us 0.1s 0.1s 0.1s 1us 1 clock -c2c jitter absper min -ssc short-term average min - ppm long-term average min 0 ppm period nominal + ppm long-term average ma x +ssc short-term average ma x +c2c jitter absper max dif 100.00 9.94900 9.99900 10.00000 10.00100 10.05100 ns 1,2 measurement wi ndow units ssc off center freq. mhz notes 1 clock 1us 0.1s 0.1s 0.1s 1us 1 clock -c2c jitter absper min -ssc short-term average min - ppm long-term average min 0 ppm period nominal + ppm long-term average ma x +ssc short-term average ma x +c2c jitter absper max dif 99.75 9.94906 9.99906 10.02406 10.02506 10.02607 10.05107 10.10107 ns 1,2 1 guaranteed by design and characterization, not 100% tested in production. 2 all long term accuracy and clock period specifications are guaranteed assuming that ref is trimmed to 25.00 mhz measurement wi ndow units ssc on center freq. mhz notes
9fgv0431 4-output very low power pcie gen 1-2-3-4 clock generator idt? 4-output very low power pcie gen 1-2-3-4 clock generator 9 9fgv0431 june 22, 2017 general smbus serial interface information how to write ? controller (host) sends a start bit ? controller (host) sends the write address ? idt clock will acknowledge ? controller (host) sends the beginning byte location = n ? idt clock will acknowledge ? controller (host) sends the byte count = x ? idt clock will acknowledge ? controller (host) starts sending byte n through byte n+x-1 ? idt clock will acknowledg e each byte one at a time ? controller (host) sends a stop bit note: read/write address is latched on sadr pin. how to read ? controller (host) will send a start bit ? controller (host) sends the write address ? idt clock will acknowledge ? controller (host) sends the beginning byte location = n ? idt clock will acknowledge ? controller (host) will send a separate start bit ? controller (host) sends the read address ? idt clock will acknowledge ? idt clock will send the data byte count = x ? idt clock sends byte n+x-1 ? idt clock sends byte 0 through byte x (if x (h) was written to byte 8) ? controller (host) will need to acknowledge each byte ? controller (host) will send a not acknowledge bit ? controller (host) will send a stop bit index block write operation controller (host) idt (slave/receiver) tstart bit slave address wr write ack beginning byte = n ack data byte count = x ack beginning byte n x byte ack o o o o o o byte n + x - 1 ack pstop bit index block read operation controller (host) idt (slave/receiver) tstart bit slave address wr write ack beginning byte = n ack rt repeat start slave address rd read ack data byte count=x ack x byte beginning byte n ack o o o o o o byte n + x - 1 n not acknowledge pstop bit
9fgv0431 4-output very low power pcie gen 1-2-3-4 clock generator idt? 4-output very low power pcie gen 1-2-3-4 clock generator 10 9fgv0431 june 22, 2017 smbus table: output enable register byte 0 name control function type 0 1 default bit 7 1 bit 6 1 bit 5 1 bit 4 1 bit 3 dif oe3 output enable rw low/low enabled 1 bit 2 dif oe3 output enable rw low/low enabled 1 bit 1 dif oe2 output enable rw low/low enabled 1 bit 0 dif oe1 output enable rw low/low enabled 1 smbus table: ss readback and vhigh control register byte 1 name control function type 0 1 default bit 7 ssenrb1 ss enable readback bit1 r latch bit 6 ssenrb1 ss enable readback bit0 r latch bit 5 ssen_swcntrl enable sw control of ss rw ss control locked values in b1[4:3] control ss amount. 0 bit 4 ssensw1 ss enable software ctl bit1 rw 1 0 bit 3 ssensw0 ss enable software ctl bit0 rw 1 0 bit 2 1 bit 1 amplitude 1 rw 00 = 0.6v 01 = 0.7v 1 bit 0 amplitude 0 rw 10= 0.8v 11 = 0.9v 0 1. b1[5] must be set to a 1 for these bits to have any effect on the part. smbus table: dif slew rate control register byte 2 name control function type 0 1 default bit 7 1 bit 6 1 bit 5 1 bit 4 1 bit 3 slewratesel dif3 adjust slew rate of dif3 rw 2.0v/ns 3.0v/ns 1 bit 2 slewratesel dif2 adjust slew rate of dif2 rw 2.0v/ns 3.0v/ns 1 bit 1 slewratesel dif1 adjust slew rate of dif3 rw 2.0v/ns 3.0v/ns 1 bit 0 slewratesel dif0 adjust slew rate of dif1 rw 2.0v/ns 3.0v/ns 1 smbus table: ref control register byte 3 name control function type 0 1 default bit 7 rw 00 = 0.9v/ns 01 =1.3v/ns 0 bit 6 rw 10 = 1.6v/ns 11 = 1.8v/ns 1 bit 5 ref power down function wake-on-lan enable for ref rw ref does not run in power down ref runs in power down 0 bit 4 ref oe ref output enable rw low enabled 1 bit 3 1 bit 2 1 bit 1 1 bit 0 1 byte 4 is reserved and reads back 'hff'. reserved reserved reserved reserved reserved reserved 00' = ss off, '01' = -0.25% ss, '10' = reserved, '11'= -0.5% ss 00' for ss_en_tri = 0, '01' for ss_en_tri = 'm', '11 for ss_en_tri = '1' reserved reserved reserved reserved ref reserved controls output amplitude slew rate control reserved reserved
9fgv0431 4-output very low power pcie gen 1-2-3-4 clock generator idt? 4-output very low power pcie gen 1-2-3-4 clock generator 11 9fgv0431 june 22, 2017 recommended crystal charac teristics (3225 package) smbus table: revision and vendor id register byte 5 name control function type 0 1 default bit 7 rid3 r 0 bit 6 rid2 r 0 bit 5 rid1 r 0 bit 4 rid0 r 0 bit 3 vid3 r 0 bit 2 vid2 r 0 bit 1 vid1 r 0 bit 0 vid0 r 1 smbus table: device type/device id byte 6 name control function type 0 1 default bit 7 device type1 r 0 bit 6 device type0 r 0 bit 5 device id5 r 0 bit 4 device id4 r 0 bit 3 device id3 r 0 bit 2 device id2 r 1 bit 1 device id1 r 0 bit 0 device id0 r 0 smbus table: byte count register byte 7 name control function type 0 1 default bit 7 0 bit 6 0 bit 5 0 bit 4 bc4 rw 0 bit 3 bc3 rw 1 bit 2 bc2 rw 0 bit 1 bc1 rw 0 bit 0 bc0 rw 0 a rev = 0000 vendor id revision id reserved 0001 = idt 000100 binary or 04 hex 00 = fgv, 01 = dbv, 10 = dmv, 11= reserved device type byte count programming reserved device id reserved writing to this register will configure how many bytes will be read back, default is = 8 bytes. parameter value units notes frequency 25 mhz 1 resonance mode fundamental - 1 frequency tolerance @ 25c 20 ppm max 1 frequency stability, ref @ 25c over operating temperature range 20 ppm max 1 temperature range (commercial) 0~70 c 1 temperature range (industrial) -40~85 c 2 equivalent series resistance (esr) 50 ? max 1 shunt capacitance (c o )7pf max1 load capacitance (c l )8pf max1 drive level 0.3 mw max 1 aging per year 5 ppm max 1 notes: 1. fox 603-25-150. 2. for i-temp, fox 603-25-261.
9fgv0431 4-output very low power pcie gen 1-2-3-4 clock generator idt? 4-output very low power pcie gen 1-2-3-4 clock generator 12 9fgv0431 june 22, 2017 thermal characteristics marking diagrams notes: 1. line 2 is the truncated part number. 2. ?l? denotes rohs compliant package. 3. ?i? denotes industrial temperature grade. 4. ?yyww? is the last two digits of the year and week that the part was assembled. 5. ?coo? denotes country of origin. 6. ?lot? is the lot number. parameter symbol conditions pkg typ. units notes c/w 1 c/w 1 c/w 1 c/w 1 c/w 1 ja5 junction to air, 5 m/s air flow 27 c/w 1 1 epad soldered to board thermal resistance nlg32 ics v0431ail yyww coo lot ics gv0431al yyww coo lot
9fgv0431 4-output very low power pcie gen 1-2-3-4 clock generator idt? 4-output very low power pcie gen 1-2-3-4 clock generator 13 9fgv0431 june 22, 2017 package outline and dimensions (nlg32) www.idt.com d it
9fgv0431 4-output very low power pcie gen 1-2-3-4 clock generator idt? 4-output very low power pcie gen 1-2-3-4 clock generator 14 9fgv0431 june 22, 2017 package outline and dimensions (nlg32), cont. www.idt.com d it
9fgv0431 4-output very low power pcie gen 1-2-3-4 clock generator idt? 4-output very low power pcie gen 1-2-3-4 clock generator 15 9fgv0431 june 22, 2017 ordering information ?lf? suffix to the part numb er are the pb-free configurat ion and are rohs compliant. ?a? is the device revision d esignator (will not correlate with the datasheet revision). revision history part / order number shipping packaging package temperature 9fgv0431aklf trays 32-pin mlf 0 to +70 c 9fgv0431aklft tape and reel 32-pin mlf 0 to +70 c 9FGV0431AKILF trays 32-pin mlf -40 to +85 c 9FGV0431AKILFt tape and reel 32-pin mlf -40 to +85 c rev. issue date initiator description page # e 10/18/2016 rdw removed idt crystal part numbe r f 6/22/2017 rg updated front page gendes to reflect the pcie gen4 updates. updated electrical characteristics - filtered phase jitter parameters - pcie common clocked (cc) architectures and added pcie gen4 data 1,7
disclaimer integrated device technology, inc. (idt) and its aff iliated companies (herein referred to as ?idt?) reserve the righ t to modify the products and/or specifications described herein at any time, without noti ce, at idt?s sole discretion. performance specifications and op erating parameters of the described products are determined in an independent state and are not guaranteed to perform the same way when installed in cust omer products. the information contained herein is provided wit hout representation or warranty of any ki nd, whether express or implied, including, but not limited to, the suitability of idt's products for any pa rticular purpose, an implied warranty of me rchantability, or non-in fringement of the in tellectual property rights of others. this document is presented only as a guide and does not convey any license under intellectual property rights of idt or any third parties. idt's products are not intended for use in applications involving extreme environmental conditions or in life support systems o r similar devices where the failure or malfunction of an idt product can be reasonably expec ted to significantly affect th e health or safety of users. anyone using an idt product in such a manner does so at their own risk , absent an express, written agreement by idt. integrated device technology, idt and the idt logo are trademarks or registered trademarks of idt and its subsidiaries in the u nited states and other countries. other trademarks used herein are the property of idt or their respective third party owners. for datasheet type defi nitions and a glossary of common terms, visit www.idt.com/go/glossary . integrated device technology, inc.. all rights reserved. corporate headquarters integrated device technology, inc. www.idt.com for sales 800-345-7015 408-284-8200 www.idt.com/go/sales for tech support www.idt.com/go/support innovate with idt and accelerate your future netw orks. contact: www.idt.com 9fgv0431 4-output very low power pcie gen 1-2-3-4 clock generator synthesizers

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